1. Field of the Invention
The present invention relates to a row address strobe signal generating device for a semiconductor memory device, and in particular to a semiconductor memory device including a row address strobe signal generating device which can prevent a cell data from being destroyed during a data maintenance time, by sufficiently obtaining a writing time of the cell data in a high speed operation.
2. Description of the Background Art
FIG. 1 is a block diagram illustrating a general row address strobe signal generating device. As shown therein, the row address strobe signal generating device includes: an auto-precharge control unit 1 outputting an auto-precharge signal APCG according to an externally-inputted write auto-precharge signal WRWP; a control unit 2 generating a row address strobe precharge signal RAS-PCG according to the auto-precharge signal APCG; and a row address strobe signal generating unit 3 generating a row address strobe signal RAS enabled according to an externally-inputted active signal ACT, and disabled according to the row address strobe precharge signal RAS-PCG.
The operation of the row address strobe signal generating device will now be described with reference to the accompanying operational timing diagrams.
When the active signal ACT is enabled as shown in FIG. 2(b) at a rising edge of an externally-inputted clock signal CLK as shown in FIG. 2(a), the row address strobe signal generating unit 3 is driven, and thus the row address strobe signal RAS is enabled as shown in FIG. 2(e).
Thereafter, a write operation is performed according to row path related signals generated in a chip in relation to the row address strobe signal RAS, thereby storing the data in a memory cell.
In addition, the active signal ACT is enabled as shown in FIG. 2(b). The write auto-precharge signal WRWP is enabled after a predetermined time tRCD as shown in FIG. 2(g), and inputted to the auto-precharge control unit 1.
The data stored in the memory cell is outputted externally from the chip through a data bus line according to a pulse of an externally-inputted column address strobe signal CAS and an inside column address strobe signal ICAS.
Here, as illustrated in FIGS. 2(c) and 2(d), when it is presumed that a burst length is set to be 4, four data are consecutively outputted from an output driver.
Thereafter, as depicted in FIGS. 2(e) and 2(f), when the auto-precharge signal APCG is generated from the auto-precharge control unit 1, and inputted to the control unit 2, the control unit 2 generates the row address strobe precharge signal RAS-PCG. The row address strobe precharge signal RAS-PCG is inputted to the row address strobe signal generating unit 3 through a feedback loop, thus disabling the row address strobe signal RAS.
At this time, the auto-precharge signal APCG outputted from the auto-precharge control unit 1 is generated at a clock when a last write command is inputted or a succeeding clock.
In the case that the row address strobe signal RAS is disabled, a word line is disabled, and thus the write operation is not performed on the memory cell.
Accordingly, as shown in FIG. 2, a time of writing the data in the memory cell is a predetermined time T1.
However, since the semiconductor memory device is operated at a high frequency, the write operation is not finished for a data maintenance time. As a result, the data may be lost for the data writing time.